In the past, there has been known a parallel computer system in which a plurality of information processing apparatuses (nodes) performs mutual data transmission and reception and performs arithmetic processing. As an example of such a parallel computer system, there is known a parallel computer system that mutually connects a plurality of information processing apparatuses, which does not share a memory space, to one another through a mutual connection network.
The information processing apparatus included in the parallel computer system includes a main memory that is a main storage device storing data to be used in an arithmetic operation, an arithmetic processing unit that performs the arithmetic operation, and a network interface (communication device) that performs transmission and reception of data used in the arithmetic operation between other information processing apparatuses. The network interface used in the information processing apparatus performs transmission and reception of data related to the arithmetic operation with another information processing apparatus through the mutual connection network and stores the received data in the main memory. Here, when a cache line of a processor corresponding to an address of a written main memory is valid, processing of invalidating the cache line is needed for maintaining consistency of the main memory and the cache memory.